FPGA Design and Implementation

Chapter/Topic 1:

Introduction to FPGA:

Chapter/Topic 2 (Part-1):

FPGA Software and First Example:

  • List of top FPGA companies/ manufacturers/ providers
  • Some common applications of FPGA
  • Generic design flow of an FPGA application or project
  • Brief introduction to Altera/Intel MAX 10 FPGA Development Kit
  • Software’s for Altera/Intel FPGAs and their installation process

Important Links:

Chapter/Topic 2 (Part-2):

FPGA Software and First Example:

  • Difference between Verilog and VHDL
  • Verilog code for Inverter (or NOT gate) logic and its test bench
  • Simulation of Inverter logic in Modelsim
  • Verilog code synthesis in Quartus Prime Lite edition
  • How to upload the bitstream to Altera/Intel MAX 10 FPGA Development Kit
  • Finally, demonstration of the project in Altera/Intel MAX 10 FPGA Development Kit

Lecture video is available here.

Chapter/Topic 3 (Part-1):

Introduction to Verilog:

  • What is Verilog
  • Explanation of basic syntax of Verilog
  • What is module and how it works
  • Discusses two Verilog examples (AND Gate and Two Level Logic)
  • Simulation of Two Level Logic example in Modelsim and its implementation in MAX 1o Development Kit

Lecture video is available here.

Chapter/Topic 3 (Part-2):

Introduction to Verilog:

  • Behavioral vs Structural description
  • Variable data types
  • Constant values
  • Parameters
  • Simulation of LED blink (or toggle) example in Modelsim and its implementation in MAX 1o Development Kit using the on-board 50 MHz oscillator. The Verilog code uses clock divider to reduce the clock speed.

Lecture video is available here.

Chapter/Topic 3 (Part-3):

Introduction to Verilog:

  • Verilog logic values
  • Primitive gates
  • Verilog operators
    • Simulation of 4-bit Counter example in Modelsim and its implementation in MAX 1o Development Kit using the on-board 50 MHz oscillator. The Verilog code uses clock divider to reduce the clock speed.

    Lecture video is available here.

    Chapter/Topic 3 (Part-4):

    Introduction to Verilog:

    • Always block basic
    • Test bench basic and Initial block
    • Blocking and Non-blocking assignments
      • Simulation of 4-bit Ring Counter example in Modelsim and its implementation in MAX 1o Development Kit using the on-board 50 MHz oscillator. The Verilog code uses clock divider to reduce the clock speed.

      Lecture video is available here.

      Stay tuned for future chapters of this course.